{
struct device_node *np;
void __iomem *base;
+ bool lcdif1_assigned_clk;
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
IMX6SX_CLK_CLK_END), GFP_KERNEL);
clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk);
clk_set_rate(hws[IMX6SX_CLK_EIM_SLOW]->clk, 132000000);
- /* set parent clock for LCDIF1 pixel clock */
- clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk);
- clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, hws[IMX6SX_CLK_LCDIF1_PODF]->clk);
+ np = of_find_node_by_path("/soc/bus@2200000/spba-bus@2240000/lcdif@2220000");
+ lcdif1_assigned_clk = of_find_property(np, "assigned-clock-parents", NULL);
+
+ /* Set parent clock for LCDIF1 pixel clock if not done via devicetree */
+ if (!lcdif1_assigned_clk) {
+ clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk,
+ hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk);
+ clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk,
+ hws[IMX6SX_CLK_LCDIF1_PODF]->clk);
+ }
/* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
if (clk_set_parent(hws[IMX6SX_CLK_LVDS1_SEL]->clk, hws[IMX6SX_CLK_PCIE_REF_125M]->clk))