drm/i915/display: Abstract C10/C20 pll calculation

As done with the hw readout, properly abstract the C10/C20 phy details
inside intel_cx0_phy.c.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231018222831.4132968-3-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6fa91acc0a25c8a3efef5b9f429765a418045d2a..b2ad4c6172f6c84b3f514cbf330ad186eaaac28f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2392,8 +2392,8 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
                      BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
 }
 
-int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
-                                const struct intel_c10pll_state *pll_state)
+static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
+                                       const struct intel_c10pll_state *pll_state)
 {
        unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
        unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
@@ -2419,8 +2419,8 @@ int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
        return tmpclk;
 }
 
-int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
-                                const struct intel_c20pll_state *pll_state)
+static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+                                       const struct intel_c20pll_state *pll_state)
 {
        unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
        unsigned int multiplier, refclk = 38400;
@@ -3079,3 +3079,15 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
        else
                intel_c20pll_readout_hw_state(encoder, &pll_state->c20);
 }
+
+int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
+                                const struct intel_cx0pll_state *pll_state)
+{
+       struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+       enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+       if (intel_is_c10phy(i915, phy))
+               return intel_c10pll_calc_port_clock(encoder, &pll_state->c10);
+
+       return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);
+}

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index ff7ccb7855aad2403d18e16ef5fc961e9b7f5b0a..222aed16e739ffdda628bdae6fe3b2c0bba7fd8d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -33,17 +33,15 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
                                   struct intel_cx0pll_state *pll_state);
+int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
+                                const struct intel_cx0pll_state *pll_state);
 
 void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv,
                                const struct intel_c10pll_state *hw_state);
-int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
-                                const struct intel_c10pll_state *pll_state);
 void intel_c10pll_state_verify(struct intel_atomic_state *state,
                               struct intel_crtc *crtc);
 void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
                                const struct intel_c20pll_state *hw_state);
-int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
-                                const struct intel_c20pll_state *pll_state);
 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
                                     const struct intel_crtc_state *crtc_state);
 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 80a8ab7874db4677d83881b4e1a0e7e8272153e2..c4dc1f71da4bc49de0c47e60dff8492f436731c4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3854,18 +3854,13 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
 static void mtl_ddi_get_config(struct intel_encoder *encoder,
                               struct intel_crtc_state *crtc_state)
 {
-       struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-       enum phy phy = intel_port_to_phy(i915, encoder->port);
        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
        if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
                crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
-       } else if (intel_is_c10phy(i915, phy)) {
-               intel_cx0pll_readout_hw_state(encoder, &crtc_state->cx0pll_state);
-               crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
        } else {
                intel_cx0pll_readout_hw_state(encoder, &crtc_state->cx0pll_state);
-               crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
+               crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state);
        }
 
        intel_ddi_get_config(encoder, crtc_state);

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index d41c1dc9f66c6580e8954ad91012a05d41a801c2..509b862f9e60721279c45786ecb918c41a92913c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1003,12 +1003,10 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
 static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
                                  struct intel_crtc *crtc)
 {
-       struct drm_i915_private *i915 = to_i915(state->base.dev);
        struct intel_crtc_state *crtc_state =
                intel_atomic_get_new_crtc_state(state, crtc);
        struct intel_encoder *encoder =
                intel_get_crtc_new_encoder(state, crtc_state);
-       enum phy phy = intel_port_to_phy(i915, encoder->port);
        int ret;
 
        ret = intel_cx0pll_calc_state(crtc_state, encoder);
@@ -1016,10 +1014,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
                return ret;
 
        /* TODO: Do the readback via intel_compute_shared_dplls() */
-       if (intel_is_c10phy(i915, phy))
-               crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
-       else
-               crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
+       crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state);
 
        crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);