drm/amd/display: Add DCC/Tiling reset helper for DCN and DCE

This commit introduces a function helper for resetting DCN/DCE DCC and
tiling. Those functions are generic for their respective DCN/DCE, so
they were added to the oldest version of each architecture.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
index f1f14796a3da3ed394c4c509b23db2b578728ee6..b76350a9cf5f59bb4738c79c2119fb7c39b97fb1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
@@ -140,3 +140,32 @@ void dce100_hw_sequencer_construct(struct dc *dc)
        dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
 }
 
+/**
+ * dce100_reset_surface_dcc_and_tiling - Set DCC and tiling in DCE to their disable mode.
+ *
+ * @pipe_ctx: Pointer to the pipe context structure.
+ * @plane_state: Surface state
+ * @clear_tiling: If true set tiling to Linear, otherwise does not change tiling
+ *
+ * This function is responsible for call the HUBP block to disable DCC and set
+ * tiling to the linear mode.
+ */
+void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,
+                                       struct dc_plane_state *plane_state,
+                                       bool clear_tiling)
+{
+       struct mem_input *mi = pipe_ctx->plane_res.mi;
+
+       if (!mi)
+               return;
+
+       /* if framebuffer is tiled, disable tiling */
+       if (clear_tiling && mi->funcs->mem_input_clear_tiling)
+               mi->funcs->mem_input_clear_tiling(mi);
+
+       /* force page flip to see the new content of the framebuffer */
+       mi->funcs->mem_input_program_surface_flip_and_addr(mi,
+                                                          &plane_state->address,
+                                                          true);
+}
+

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h
index 34518da20009d94ede9c8f725e99c516688704aa..fadfa794f96bba1f3e4c7bfb7f1e11a90a7a53ef 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h
@@ -46,5 +46,9 @@ bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
                                        struct dc_bios *dcb,
                                        enum pipe_gating_control power_gating);
 
+void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,
+                                       struct dc_plane_state *plane_state,
+                                       bool clear_tiling);
+
 #endif /* __DC_HWSS_DCE100_H__ */
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 35c0d101d7c8eaba07f2ac50ca5bcbfdb3bddab5..301ef36d3d05d957d570c075e1df9bbbadfa43ba 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -3920,3 +3920,32 @@ void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits)
                        dcc_en_bits[i] = s->dcc_en ? 1 : 0;
        }
 }
+
+/**
+ * dcn10_reset_surface_dcc_and_tiling - Set DCC and tiling in DCN to their disable mode.
+ *
+ * @pipe_ctx: Pointer to the pipe context structure.
+ * @plane_state: Surface state
+ * @clear_tiling: If true set tiling to Linear, otherwise does not change tiling
+ *
+ * This function is responsible for call the HUBP block to disable DCC and set
+ * tiling to the linear mode.
+ */
+void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,
+                                       struct dc_plane_state *plane_state,
+                                       bool clear_tiling)
+{
+       struct hubp *hubp = pipe_ctx->plane_res.hubp;
+
+       if (!hubp)
+               return;
+
+       /* if framebuffer is tiled, disable tiling */
+       if (clear_tiling && hubp->funcs->hubp_clear_tiling)
+               hubp->funcs->hubp_clear_tiling(hubp);
+
+       /* force page flip to see the new content of the framebuffer */
+       hubp->funcs->hubp_program_surface_flip_and_addr(hubp,
+                                                       &plane_state->address,
+                                                       true);
+}

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
index bc5dd68a2408801d0e9f46373e523e1dab01c461..42ffd1e1299c856f619278e67248b5edde117d68 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
@@ -207,4 +207,8 @@ void dcn10_update_visual_confirm_color(
                struct pipe_ctx *pipe_ctx,
                int mpcc_id);
 
+void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,
+                                       struct dc_plane_state *plane_state,
+                                       bool clear_tiling);
+
 #endif /* __DC_HWSS_DCN10_H__ */