clk: tegra: Return the exact clock rate from clk_round_rate

The current behavior is that clk_round_rate would return the same clock
rate passed to it for valid PLL configurations. This change will return
the exact rate the PLL will provide in accordance with clk API.

Signed-off-by: Robert Yang <decatf@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 830d1c87fa7cb6d089ff95992a3e2592691801ea..b50b7460014bcd8452622907cf9c64c35f0a155c 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -590,12 +590,13 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
        cfg->n = cfg->output_rate / cfreq;
        cfg->cpcon = OUT_OF_TABLE_CPCON;
 
-       if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
-           (1 << p_div) > divp_max(pll)
-           || cfg->output_rate > pll->params->vco_max) {
+       if (cfg->m == 0 || cfg->m > divm_max(pll) ||
+           cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
+           cfg->output_rate > pll->params->vco_max) {
                return -EINVAL;
        }
 
+       cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
        cfg->output_rate >>= p_div;
 
        if (pll->params->pdiv_tohw) {