scsi: ufs: qcom: Update MAX_CORE_CLK_1US_CYCLES for UFS V4 and above

UFS Controller V4 and above, the register layout for DME_VS_CORE_CLK_CTRL
register has changed. MAX_CORE_CLK_1US_CYCLES offset has changed from 0 to
0x10 and length of attrbute is changed from 8bit to 12bit.

Add support to configure MAX_CORE_CLK_1US_CYCLES for UFS V4 and above as
per new register layout.

Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Link: https://lore.kernel.org/r/20230905052400.13935-2-quic_nitirawa@quicinc.com
Reviewed-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index d1149b1c3ed50e4220227ddde7e0f9bc13e883f6..d846e68a5734c38be843522e900f525b8d44246b 100644 (file)
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1299,20 +1299,28 @@ static void ufs_qcom_exit(struct ufs_hba *hba)
 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
                                                       u32 clk_cycles)
 {
+       struct ufs_qcom_host *host = ufshcd_get_variant(hba);
        int err;
        u32 core_clk_ctrl_reg;
 
-       if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
-               return -EINVAL;
-
        err = ufshcd_dme_get(hba,
                            UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
                            &core_clk_ctrl_reg);
        if (err)
                return err;
 
-       core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
-       core_clk_ctrl_reg |= clk_cycles;
+       /* Bit mask is different for UFS host controller V4.0.0 onwards */
+       if (host->hw_ver.major >= 4) {
+               if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, clk_cycles))
+                       return -ERANGE;
+               core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
+               core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, clk_cycles);
+       } else {
+               if (!FIELD_FIT(CLK_1US_CYCLES_MASK, clk_cycles))
+                       return -ERANGE;
+               core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
+               core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, clk_cycles);
+       }
 
        /* Clear CORE_CLK_DIV_EN */
        core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;

diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index d6f8e74bd5381c8b7473179fda57b79c7bab607e..8a9d3dbec2973265fa5f540e5539e15b2af71733 100644 (file)
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -129,8 +129,9 @@ enum {
 #define PA_VS_CONFIG_REG1      0x9000
 #define DME_VS_CORE_CLK_CTRL   0xD002
 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
-#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT               BIT(8)
-#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK      0xFF
+#define CLK_1US_CYCLES_MASK_V4                         GENMASK(27, 16)
+#define CLK_1US_CYCLES_MASK                            GENMASK(7, 0)
+#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT       BIT(8)
 
 static inline void
 ufs_qcom_get_controller_revision(struct ufs_hba *hba,