drm/msm/dpu: drop the regdma configuration
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 20 Apr 2023 22:25:57 +0000 (01:25 +0300)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Mon, 22 May 2023 07:14:16 +0000 (10:14 +0300)
The regdma is currently not used by the current driver. We have no way
to practically verify that the regdma is described correctly. Drop it
now.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/533148/
Link: https://lore.kernel.org/r/20230420222558.1208887-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
12 files changed:
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

index 9116129527797d9be7f72b3b4769d3459c193e5c..4cd8d7871c4a212f0cc0dc81b6fc5cdb7918f279 100644 (file)
@@ -195,7 +195,6 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
        .intf = msm8998_intf,
        .vbif_count = ARRAY_SIZE(msm8998_vbif),
        .vbif = msm8998_vbif,
-       .reg_dma_count = 0,
        .perf = &msm8998_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index ceca741e93c9b812af8a52fe6bffa6685ad8b6d6..63009435e258872c40c61cc48e7c5ac2bbc73860 100644 (file)
@@ -193,8 +193,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
        .intf = sdm845_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sdm845_regdma,
        .perf = &sdm845_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 42b0e58624d0087c5760f710021c1758e46b3fdd..b3f67710a48deca0708bd321298b5518946e2959 100644 (file)
@@ -220,8 +220,6 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
        .intf = sm8150_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8150_regdma,
        .perf = &sm8150_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 3911ae4925404f5014dab6fe456013961ac40184..1aef11a258346b7569445b245b594ee8b7552c77 100644 (file)
@@ -222,8 +222,6 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
        .intf = sc8180x_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8150_regdma,
        .perf = &sc8180x_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index ed130582873c7037294dccdd6798fa66bc0948de..903efc580aef00f188bddd131418df3c980711b7 100644 (file)
@@ -228,8 +228,6 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
        .vbif = sdm845_vbif,
        .wb_count = ARRAY_SIZE(sm8250_wb),
        .wb = sm8250_wb,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8250_regdma,
        .perf = &sm8250_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index a46b11730a4d4a2c43a295ade916b75b158328a4..3ab5fbada08fa887d89b32bab8e3d8697bae4ead 100644 (file)
@@ -143,8 +143,6 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
        .wb = sc7180_wb,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sdm845_regdma,
        .perf = &sc7180_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 4f6a965bcd90b187a99146d74bdc9f3c4ca32dd6..9e8d6632a1927adf2c0cdb3b9937c819a7512960 100644 (file)
@@ -211,8 +211,6 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
        .intf = sm8350_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8350_regdma,
        .perf = &sm8350_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 88b8226e6f75d1df9c8c7c22400ddf460b5c1ae1..8e4d0bc4aa7038ca95ba0ccb8c6bcffafb0756a2 100644 (file)
@@ -203,8 +203,6 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
        .intf = sc8280xp_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sc8280xp_regdma,
        .perf = &sc8280xp_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index cb83d25834ceb61a5f0fc651801964e2c3d58f7f..014922ac03dbc2fc20a21f3232e1ca5da42e8390 100644 (file)
@@ -219,8 +219,6 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
        .intf = sm8450_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8450_regdma,
        .perf = &sm8450_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index d0ab351b6a8b934226fded7bdcf9db3ee30ac80a..be2f37728aa0cf0a15caaf8009d99f2c5a55e384 100644 (file)
@@ -224,8 +224,6 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
        .intf = sm8550_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),
        .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8450_regdma,
        .perf = &sm8550_perf_data,
        .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
                     BIT(MDP_SSPP_TOP0_INTR2) | \
index 5d994bce696f9e76e6387aa1bf66bc8c6cbac298..afe667121dc796ddc88dad660526b97c4c5f5f54 100644 (file)
@@ -650,46 +650,6 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
        },
 };
 
-static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
-       .base = 0x0,
-       .version = 0x00020000,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
-static const struct dpu_reg_dma_cfg sdm845_regdma = {
-       .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
-};
-
-static const struct dpu_reg_dma_cfg sm8150_regdma = {
-       .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
-};
-
-static const struct dpu_reg_dma_cfg sm8250_regdma = {
-       .base = 0x0,
-       .version = 0x00010002,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
-static const struct dpu_reg_dma_cfg sm8350_regdma = {
-       .base = 0x400,
-       .version = 0x00020000,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
-static const struct dpu_reg_dma_cfg sm8450_regdma = {
-       .base = 0x0,
-       .version = 0x00020000,
-       .trigger_sel_off = 0x119c,
-       .xin_id = 7,
-       .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
-};
-
 /*************************************************************
  * PERF data config
  *************************************************************/
index 71584cd56fd759c2a2a6a792f7d76c42f2babb2e..8d62c21b051a8f70a547a485c36a6357efe9b54c 100644 (file)
@@ -720,21 +720,6 @@ struct dpu_vbif_cfg {
        u32 memtype_count;
        u32 memtype[MAX_XIN_COUNT];
 };
-/**
- * struct dpu_reg_dma_cfg - information of lut dma blocks
- * @id                 enum identifying this block
- * @base               register offset of this block
- * @features           bit mask identifying sub-blocks/features
- * @version            version of lutdma hw block
- * @trigger_sel_off    offset to trigger select registers of lutdma
- */
-struct dpu_reg_dma_cfg {
-       DPU_HW_BLK_INFO;
-       u32 version;
-       u32 trigger_sel_off;
-       u32 xin_id;
-       enum dpu_clk_ctrl_type clk_ctrl;
-};
 
 /**
  * Define CDP use cases
@@ -850,9 +835,6 @@ struct dpu_mdss_cfg {
        u32 wb_count;
        const struct dpu_wb_cfg *wb;
 
-       u32 reg_dma_count;
-       const struct dpu_reg_dma_cfg *dma_cfg;
-
        u32 ad_count;
 
        u32 dspp_count;