arm64: dts: imx8: correct clock order

Per bindings/mmc/fsl-imx-esdhc.yaml, the clock order is ipg, ahb, per,
otherwise warning: "
mmc@5b020000: clock-names:1: 'ahb' was expected
mmc@5b020000: clock-names:2: 'per' was expected "

Fixes: 16c4ea7501b1 ("arm64: dts: imx8: switch to new lpcg clock binding")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 82a1c448837861988feb0b9570db6aef544e2c89..10370d1a6c6defebd3b83e83f3188d79473eefc2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -38,9 +38,9 @@ conn_subsys: bus@5b000000 {
                interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
                reg = <0x5b010000 0x10000>;
                clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
-                        <&sdhc0_lpcg IMX_LPCG_CLK_5>,
-                        <&sdhc0_lpcg IMX_LPCG_CLK_0>;
-               clock-names = "ipg", "per", "ahb";
+                        <&sdhc0_lpcg IMX_LPCG_CLK_0>,
+                        <&sdhc0_lpcg IMX_LPCG_CLK_5>;
+               clock-names = "ipg", "ahb", "per";
                power-domains = <&pd IMX_SC_R_SDHC_0>;
                status = "disabled";
        };
@@ -49,9 +49,9 @@ conn_subsys: bus@5b000000 {
                interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
                reg = <0x5b020000 0x10000>;
                clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
-                        <&sdhc1_lpcg IMX_LPCG_CLK_5>,
-                        <&sdhc1_lpcg IMX_LPCG_CLK_0>;
-               clock-names = "ipg", "per", "ahb";
+                        <&sdhc1_lpcg IMX_LPCG_CLK_0>,
+                        <&sdhc1_lpcg IMX_LPCG_CLK_5>;
+               clock-names = "ipg", "ahb", "per";
                power-domains = <&pd IMX_SC_R_SDHC_1>;
                fsl,tuning-start-tap = <20>;
                fsl,tuning-step = <2>;
@@ -62,9 +62,9 @@ conn_subsys: bus@5b000000 {
                interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
                reg = <0x5b030000 0x10000>;
                clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
-                        <&sdhc2_lpcg IMX_LPCG_CLK_5>,
-                        <&sdhc2_lpcg IMX_LPCG_CLK_0>;
-               clock-names = "ipg", "per", "ahb";
+                        <&sdhc2_lpcg IMX_LPCG_CLK_0>,
+                        <&sdhc2_lpcg IMX_LPCG_CLK_5>;
+               clock-names = "ipg", "ahb", "per";
                power-domains = <&pd IMX_SC_R_SDHC_2>;
                status = "disabled";
        };