arm64: dts: qcom: sm8150: Define CPU topology

sm8150 has a big.LITTLE CPU setup with DynamIQ, so all cores are within
the same CPU cluster and LLC (Last-Level Cache) domain. Define this
topology to help the scheduler make decisions.

Signed-off-by: Danny Lin <danny@kdrag0n.dev>
Link: https://lore.kernel.org/r/20201221002907.2870059-2-danny@kdrag0n.dev
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 5270bda7418f048a15450ea09de8dcb985f32705..d2159b1aa97e14d21e15aa4aa1bf7539e83872e0 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -157,6 +157,42 @@
                                next-level-cache = <&L3_0>;
                        };
                };
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&CPU0>;
+                               };
+
+                               core1 {
+                                       cpu = <&CPU1>;
+                               };
+
+                               core2 {
+                                       cpu = <&CPU2>;
+                               };
+
+                               core3 {
+                                       cpu = <&CPU3>;
+                               };
+
+                               core4 {
+                                       cpu = <&CPU4>;
+                               };
+
+                               core5 {
+                                       cpu = <&CPU5>;
+                               };
+
+                               core6 {
+                                       cpu = <&CPU6>;
+                               };
+
+                               core7 {
+                                       cpu = <&CPU7>;
+                               };
+                       };
+               };
        };
 
        firmware {