arm64: dts: imx8m: correct assigned clocks for FEC

commit 70eacf42a93aff6589a8b91279bbfe5f73c4ca3d upstream.

CLK_ENET_TIMER assigned clocks twice, should be a typo, correct to
CLK_ENET_PHY_REF clock.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 05ee062548e4fc2aca21e654aedf1ad7a89d9fce..f4d7bb75707df286168bf0a1c5a004f7d15bf961 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -866,11 +866,12 @@
                                assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
                                                  <&clk IMX8MM_CLK_ENET_TIMER>,
                                                  <&clk IMX8MM_CLK_ENET_REF>,
-                                                 <&clk IMX8MM_CLK_ENET_TIMER>;
+                                                 <&clk IMX8MM_CLK_ENET_PHY_REF>;
                                assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
                                                         <&clk IMX8MM_SYS_PLL2_100M>,
-                                                        <&clk IMX8MM_SYS_PLL2_125M>;
-                               assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+                                                        <&clk IMX8MM_SYS_PLL2_125M>,
+                                                        <&clk IMX8MM_SYS_PLL2_50M>;
+                               assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
                                fsl,num-tx-queues = <3>;
                                fsl,num-rx-queues = <3>;
                                status = "disabled";

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 16c7202885d7094bdc03f0a07188a3a7e2d17c54..aea723eb2ba3f42b72b0f49f22aa545d30f6b3ac 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -753,11 +753,12 @@
                                assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
                                                  <&clk IMX8MN_CLK_ENET_TIMER>,
                                                  <&clk IMX8MN_CLK_ENET_REF>,
-                                                 <&clk IMX8MN_CLK_ENET_TIMER>;
+                                                 <&clk IMX8MN_CLK_ENET_PHY_REF>;
                                assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
                                                         <&clk IMX8MN_SYS_PLL2_100M>,
-                                                        <&clk IMX8MN_SYS_PLL2_125M>;
-                               assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+                                                        <&clk IMX8MN_SYS_PLL2_125M>,
+                                                        <&clk IMX8MN_SYS_PLL2_50M>;
+                               assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
                                fsl,num-tx-queues = <3>;
                                fsl,num-rx-queues = <3>;
                                status = "disabled";

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 03ef0e5f909e478649f70638168b05bc29555821..acee71ca32d83ebdbbe9685f689661db368f6e52 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -725,11 +725,12 @@
                                assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
                                                  <&clk IMX8MP_CLK_ENET_TIMER>,
                                                  <&clk IMX8MP_CLK_ENET_REF>,
-                                                 <&clk IMX8MP_CLK_ENET_TIMER>;
+                                                 <&clk IMX8MP_CLK_ENET_PHY_REF>;
                                assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
                                                         <&clk IMX8MP_SYS_PLL2_100M>,
-                                                        <&clk IMX8MP_SYS_PLL2_125M>;
-                               assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+                                                        <&clk IMX8MP_SYS_PLL2_125M>,
+                                                        <&clk IMX8MP_SYS_PLL2_50M>;
+                               assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
                                fsl,num-tx-queues = <3>;
                                fsl,num-rx-queues = <3>;
                                status = "disabled";