}
}
- ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
- SC27XX_ADC_EN, SC27XX_ADC_EN);
+ ret = regmap_set_bits(data->regmap, data->base + SC27XX_ADC_CTL,
+ SC27XX_ADC_EN);
if (ret)
goto regulator_restore;
- ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
- SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR);
+ ret = regmap_set_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
+ SC27XX_ADC_IRQ_CLR);
if (ret)
goto disable_adc;
if (ret)
goto disable_adc;
- ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
- SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN);
+ ret = regmap_set_bits(data->regmap, data->base + SC27XX_ADC_CTL,
+ SC27XX_ADC_CHN_RUN);
if (ret)
goto disable_adc;
value &= SC27XX_ADC_DATA_MASK;
disable_adc:
- regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
- SC27XX_ADC_EN, 0);
+ regmap_clear_bits(data->regmap, data->base + SC27XX_ADC_CTL,
+ SC27XX_ADC_EN);
regulator_restore:
if ((data->var_data->set_volref) && (channel == 30 || channel == 31)) {
ret_volref = regulator_set_voltage(data->volref,
{
int ret;
- ret = regmap_update_bits(data->regmap, data->var_data->module_en,
- SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN);
+ ret = regmap_set_bits(data->regmap, data->var_data->module_en,
+ SC27XX_MODULE_ADC_EN);
if (ret)
return ret;
/* Enable ADC work clock and controller clock */
- ret = regmap_update_bits(data->regmap, data->var_data->clk_en,
- SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN,
- SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
+ ret = regmap_set_bits(data->regmap, data->var_data->clk_en,
+ SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
if (ret)
goto disable_adc;
return 0;
disable_clk:
- regmap_update_bits(data->regmap, data->var_data->clk_en,
- SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
+ regmap_clear_bits(data->regmap, data->var_data->clk_en,
+ SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
disable_adc:
- regmap_update_bits(data->regmap, data->var_data->module_en,
- SC27XX_MODULE_ADC_EN, 0);
+ regmap_clear_bits(data->regmap, data->var_data->module_en,
+ SC27XX_MODULE_ADC_EN);
return ret;
}
struct sc27xx_adc_data *data = _data;
/* Disable ADC work clock and controller clock */
- regmap_update_bits(data->regmap, data->var_data->clk_en,
- SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
+ regmap_clear_bits(data->regmap, data->var_data->clk_en,
+ SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
- regmap_update_bits(data->regmap, data->var_data->module_en,
- SC27XX_MODULE_ADC_EN, 0);
+ regmap_clear_bits(data->regmap, data->var_data->module_en,
+ SC27XX_MODULE_ADC_EN);
}
static const struct sc27xx_adc_variant_data sc2731_data = {