coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses

This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. In sysreg.h fields are defined as
the register name followed by the field name and then _MASK. This
allows for grepping for fields by name rather than using magic numbers.

Signed-off-by: James Clark <james.clark@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-13-james.clark@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 88353f8ba41446e8b272097c8ab92d7e36ca8e67..87299e99dabb96395bc75d4859bfd3acd5e6d12c 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -443,7 +443,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
        for (i = 0; i < drvdata->nr_ss_cmp; i++) {
                /* always clear status bit on restart if using single-shot */
                if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
-                       config->ss_status[i] &= ~BIT(31);
+                       config->ss_status[i] &= ~TRCSSCSRn_STATUS;
                etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
                etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
                if (etm4x_sspcicrn_present(drvdata, i))

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 29188b1a4646fd75d98eabf5f6eb0b85e97fd3ef..7dd7636fc2a7be75ef47baa34fc47cca680425c2 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -1792,9 +1792,9 @@ static ssize_t sshot_ctrl_store(struct device *dev,
 
        spin_lock(&drvdata->spinlock);
        idx = config->ss_idx;
-       config->ss_ctrl[idx] = val & GENMASK(24, 0);
+       config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
        /* must clear bit 31 in related status register on programming */
-       config->ss_status[idx] &= ~BIT(31);
+       config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
        spin_unlock(&drvdata->spinlock);
        return size;
 }
@@ -1844,7 +1844,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
        idx = config->ss_idx;
        config->ss_pe_cmp[idx] = val & GENMASK(7, 0);
        /* must clear bit 31 in related status register on programming */
-       config->ss_status[idx] &= ~BIT(31);
+       config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
        spin_unlock(&drvdata->spinlock);
        return size;
 }

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 802ddbe2eecd59fb2719b0c4e48e69a003daadbd..b4217eaab4505e998a1c68312582575e4e717ecf 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -214,6 +214,10 @@
 #define TRCACATRn_CONTEXTTYPE_VMID             BIT(3)
 #define TRCACATRn_CONTEXT_MASK                 GENMASK(6, 4)
 #define TRCACATRn_EXLEVEL_MASK                 GENMASK(14, 8)
+
+#define TRCSSCSRn_STATUS                       BIT(31)
+#define TRCSSCCRn_SAC_ARC_RST_MASK             GENMASK(24, 0)
+
 /*
  * System instructions to access ETM registers.
  * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions