arm64: dts: imx8qm-mek: add fec2 support

Add fec2 support.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 3e57c760e40a5b287aa091f8e7de1052254c1ef4..c024be33fbccea3b98e0593eb688d0868167276c 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -40,6 +40,15 @@
                enable-active-high;
        };
 
+       reg_fec2_supply: regulator-fec2-nvcc {
+               compatible = "regulator-fixed";
+               regulator-name = "fec2_nvcc";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
        reg_can01_en: regulator-can01-gen {
                compatible = "regulator-fixed";
                regulator-name = "can01-en";
@@ -334,6 +343,19 @@
        };
 };
 
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec2>;
+       phy-mode = "rgmii-txid";
+       phy-handle = <&ethphy1>;
+       phy-supply = <&reg_fec2_supply>;
+       nvmem-cells = <&fec_mac1>;
+       nvmem-cell-names = "mac-address";
+       rx-internal-delay-ps = <2000>;
+       fsl,magic-packet;
+       status = "okay";
+};
+
 &usdhc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc1>;
@@ -500,6 +522,24 @@
                >;
        };
 
+       pinctrl_fec2: fec2grp {
+               fsl,pins = <
+                       IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD             0x000014a0
+                       IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL       0x00000060
+                       IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC             0x00000060
+                       IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0           0x00000060
+                       IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1           0x00000060
+                       IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2           0x00000060
+                       IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3           0x00000060
+                       IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC             0x00000060
+                       IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL       0x00000060
+                       IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0           0x00000060
+                       IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1           0x00000060
+                       IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2           0x00000060
+                       IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3           0x00000060
+               >;
+       };
+
        pinctrl_flexcan1: flexcan0grp {
                fsl,pins = <
                        IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX                      0x21