clk: qcom: ipq8074: Add correct index for PCIe clocks

The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC,
GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group.

Move them to the gcc clock group.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1594877570-9280-1-git-send-email-sivaprak@codeaurora.org
Fixes: e7fb524cfcca ("dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
index e3e018565addf7cf3dafb53db3939f34ba5ca0fe..8e2bec1c91bf9827b138f2b3b1db324a583fa537 100644 (file)
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -230,6 +230,9 @@
 #define GCC_GP1_CLK                            221
 #define GCC_GP2_CLK                            222
 #define GCC_GP3_CLK                            223
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK             224
+#define GCC_PCIE0_RCHNG_CLK_SRC                        225
+#define GCC_PCIE0_RCHNG_CLK                    226
 
 #define GCC_BLSP1_BCR                          0
 #define GCC_BLSP1_QUP1_BCR                     1
@@ -363,8 +366,5 @@
 #define GCC_PCIE1_AHB_ARES                     129
 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES       130
 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES                131
-#define GCC_PCIE0_AXI_S_BRIDGE_CLK             132
-#define GCC_PCIE0_RCHNG_CLK_SRC                        133
-#define GCC_PCIE0_RCHNG_CLK                    134
 
 #endif