drm/amdgpu/sdma5.0: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

v2: rebase

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 50bf3b71bc93c2381db6f36408e3c25a1ad5b505..2ab670c58520a370fdcb29066f138d1d73c9c7b0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -187,8 +187,8 @@ static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u3
 
 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 {
-       switch (adev->asic_type) {
-       case CHIP_NAVI10:
+       switch (adev->ip_versions[SDMA0_HWIP]) {
+       case IP_VERSION(5, 0, 0):
                soc15_program_register_sequence(adev,
                                                golden_settings_sdma_5,
                                                (const u32)ARRAY_SIZE(golden_settings_sdma_5));
@@ -196,7 +196,7 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
                                                golden_settings_sdma_nv10,
                                                (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
                break;
-       case CHIP_NAVI14:
+       case IP_VERSION(5, 0, 2):
                soc15_program_register_sequence(adev,
                                                golden_settings_sdma_5,
                                                (const u32)ARRAY_SIZE(golden_settings_sdma_5));
@@ -204,7 +204,7 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
                                                golden_settings_sdma_nv14,
                                                (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
                break;
-       case CHIP_NAVI12:
+       case IP_VERSION(5, 0, 5):
                if (amdgpu_sriov_vf(adev))
                        soc15_program_register_sequence(adev,
                                                        golden_settings_sdma_5_sriov,
@@ -217,7 +217,7 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
                                                golden_settings_sdma_nv12,
                                                (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
                break;
-       case CHIP_CYAN_SKILLFISH:
+       case IP_VERSION(5, 0, 1):
                soc15_program_register_sequence(adev,
                                                golden_settings_sdma_cyan_skillfish,
                                                (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
@@ -248,22 +248,22 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
        const struct common_firmware_header *header = NULL;
        const struct sdma_firmware_header_v1_0 *hdr;
 
-       if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_NAVI12))
+       if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 0, 5)))
                return 0;
 
        DRM_DEBUG("\n");
 
-       switch (adev->asic_type) {
-       case CHIP_NAVI10:
+       switch (adev->ip_versions[SDMA0_HWIP]) {
+       case IP_VERSION(5, 0, 0):
                chip_name = "navi10";
                break;
-       case CHIP_NAVI14:
+       case IP_VERSION(5, 0, 2):
                chip_name = "navi14";
                break;
-       case CHIP_NAVI12:
+       case IP_VERSION(5, 0, 5):
                chip_name = "navi12";
                break;
-       case CHIP_CYAN_SKILLFISH:
+       case IP_VERSION(5, 0, 1):
                if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
                        chip_name = "cyan_skillfish2";
                else
@@ -1636,10 +1636,10 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
        if (amdgpu_sriov_vf(adev))
                return 0;
 
-       switch (adev->asic_type) {
-       case CHIP_NAVI10:
-       case CHIP_NAVI14:
-       case CHIP_NAVI12:
+       switch (adev->ip_versions[SDMA0_HWIP]) {
+       case IP_VERSION(5, 0, 0):
+       case IP_VERSION(5, 0, 2):
+       case IP_VERSION(5, 0, 5):
                sdma_v5_0_update_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE);
                sdma_v5_0_update_medium_grain_light_sleep(adev,