drm/amdgpu: enable umc 8.7 functions in gmc v10

add support for umc 8.7 initialization

add umc 8.7 source to makefile

Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 403ec3db29df50cc5ac38c4dc4bcbf619ca97c75..0ba396e9d7e4079ea0088ef8fea5625efe2a0c4c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -85,7 +85,7 @@ amdgpu-y += \
 
 # add UMC block
 amdgpu-y += \
-       umc_v6_1.o umc_v6_0.o
+       umc_v6_1.o umc_v6_0.o umc_v8_7.o
 
 # add IH block
 amdgpu-y += \

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 1a78073c2f053b6e478d661cd8a885bb8b05001e..35d21f330b0ab87995e373cc67b5f73c70915740 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -25,6 +25,7 @@
 #include "amdgpu.h"
 #include "amdgpu_atomfirmware.h"
 #include "gmc_v10_0.h"
+#include "umc_v8_7.h"
 
 #include "hdp/hdp_5_0_0_offset.h"
 #include "hdp/hdp_5_0_0_sh_mask.h"
@@ -55,6 +56,14 @@ static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
 };
 #endif
 
+static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
+                                        struct amdgpu_irq_src *src,
+                                        unsigned type,
+                                        enum amdgpu_interrupt_state state)
+{
+       return 0;
+}
+
 static int
 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                                   struct amdgpu_irq_src *src, unsigned type,
@@ -131,10 +140,20 @@ static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
        .process = gmc_v10_0_process_interrupt,
 };
 
-static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
+static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
+       .set = gmc_v10_0_ecc_interrupt_state,
+       .process = amdgpu_umc_process_ecc_irq,
+};
+
+ static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
 {
        adev->gmc.vm_fault.num_types = 1;
        adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
+
+       if (!amdgpu_sriov_vf(adev)) {
+               adev->gmc.ecc_irq.num_types = 1;
+               adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
+       }
 }
 
 /**
@@ -569,12 +588,29 @@ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
                adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
 }
 
+static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
+{
+       switch (adev->asic_type) {
+       case CHIP_SIENNA_CICHLID:
+               adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
+               adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
+               adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
+               adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
+               adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
+               adev->umc.funcs = &umc_v8_7_funcs;
+               break;
+       default:
+               break;
+       }
+}
+
 static int gmc_v10_0_early_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        gmc_v10_0_set_gmc_funcs(adev);
        gmc_v10_0_set_irq_funcs(adev);
+       gmc_v10_0_set_umc_funcs(adev);
 
        adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
        adev->gmc.shared_aperture_end =
@@ -790,6 +826,14 @@ static int gmc_v10_0_sw_init(void *handle)
        if (r)
                return r;
 
+       if (!amdgpu_sriov_vf(adev)) {
+               /* interrupt sent to DF. */
+               r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
+                                     &adev->gmc.ecc_irq);
+               if (r)
+                       return r;
+       }
+
        /*
         * Set the internal MC address mask This is the max address of the GPU's
         * internal address space.
@@ -950,6 +994,9 @@ static int gmc_v10_0_hw_init(void *handle)
        if (r)
                return r;
 
+       if (adev->umc.funcs && adev->umc.funcs->init_registers)
+               adev->umc.funcs->init_registers(adev);
+
        return 0;
 }
 
@@ -981,6 +1028,7 @@ static int gmc_v10_0_hw_fini(void *handle)
                return 0;
        }
 
+       amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
        amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
        gmc_v10_0_gart_disable(adev);