arm64: dts: juno: describe PMUs separately
authorMark Rutland <mark.rutland@arm.com>
Fri, 2 Oct 2015 09:55:06 +0000 (10:55 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Wed, 7 Oct 2015 13:25:41 +0000 (14:25 +0100)
The A57 and A53 PMUs in Juno support different events, so describe them
separately in both the Juno and Juno R1 DTs.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/boot/dts/arm/juno-r1.dts
arch/arm64/boot/dts/arm/juno.dts

index c62751153a4fc528202b4d645fc930f851aa2bc1..734e1272b19f526957e37eebd463a3af890816b7 100644 (file)
                };
        };
 
-       pmu {
-               compatible = "arm,armv8-pmuv3";
+       pmu_a57 {
+               compatible = "arm,cortex-a57-pmu";
                interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&A57_0>,
+                                    <&A57_1>;
+       };
+
+       pmu_a53 {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-affinity = <&A57_0>,
-                                    <&A57_1>,
-                                    <&A53_0>,
+               interrupt-affinity = <&A53_0>,
                                     <&A53_1>,
                                     <&A53_2>,
                                     <&A53_3>;
index d7cbdd482a61d231cbbfcff772dcf48e51e92bb2..ffa05aeab3c72158630f9831fa2764f3dd900cc5 100644 (file)
                };
        };
 
-       pmu {
-               compatible = "arm,armv8-pmuv3";
+       pmu_a57 {
+               compatible = "arm,cortex-a57-pmu";
                interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
-                            <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&A57_0>,
+                                    <&A57_1>;
+       };
+
+       pmu_a53 {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-               interrupt-affinity = <&A57_0>,
-                                    <&A57_1>,
-                                    <&A53_0>,
+               interrupt-affinity = <&A53_0>,
                                     <&A53_1>,
                                     <&A53_2>,
                                     <&A53_3>;