drm/amd/pm: Add gpu_metrics_v1_6

Add new gpu_metrics_v1_6 to acquire accumulated
throttler residencies

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 805c9d37a2b4e470ae2deaf958998f61405dc8be..a0955cfe41ce300525f4bad65f37300af6677134 100644 (file)
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -854,6 +854,95 @@ struct gpu_metrics_v1_5 {
        uint16_t                        padding;
 };
 
+struct gpu_metrics_v1_6 {
+       struct metrics_table_header     common_header;
+
+       /* Temperature (Celsius) */
+       uint16_t                        temperature_hotspot;
+       uint16_t                        temperature_mem;
+       uint16_t                        temperature_vrsoc;
+
+       /* Power (Watts) */
+       uint16_t                        curr_socket_power;
+
+       /* Utilization (%) */
+       uint16_t                        average_gfx_activity;
+       uint16_t                        average_umc_activity; // memory controller
+       uint16_t                        vcn_activity[NUM_VCN];
+       uint16_t                        jpeg_activity[NUM_JPEG_ENG];
+
+       /* Energy (15.259uJ (2^-16) units) */
+       uint64_t                        energy_accumulator;
+
+       /* Driver attached timestamp (in ns) */
+       uint64_t                        system_clock_counter;
+
+       /* Accumulation cycle counter */
+       uint32_t                        accumulation_counter;
+
+       /* Accumulated throttler residencies */
+       uint32_t                        prochot_residency_acc;
+       uint32_t                        ppt_residency_acc;
+       uint32_t                        socket_thm_residency_acc;
+       uint32_t                        vr_thm_residency_acc;
+       uint32_t                        hbm_thm_residency_acc;
+
+       /* Throttle status */
+       uint32_t                        throttle_status;
+
+       /* Clock Lock Status. Each bit corresponds to clock instance */
+       uint32_t                        gfxclk_lock_status;
+
+       /* Link width (number of lanes) and speed (in 0.1 GT/s) */
+       uint16_t                        pcie_link_width;
+       uint16_t                        pcie_link_speed;
+
+       /* XGMI bus width and bitrate (in Gbps) */
+       uint16_t                        xgmi_link_width;
+       uint16_t                        xgmi_link_speed;
+
+       /* Utilization Accumulated (%) */
+       uint32_t                        gfx_activity_acc;
+       uint32_t                        mem_activity_acc;
+
+       /*PCIE accumulated bandwidth (Mbps) */
+       uint64_t                        pcie_bandwidth_acc;
+
+       /*PCIE instantaneous bandwidth (Mbps) */
+       uint64_t                        pcie_bandwidth_inst;
+
+       /* PCIE L0 to recovery state transition accumulated count */
+       uint64_t                        pcie_l0_to_recov_count_acc;
+
+       /* PCIE replay accumulated count */
+       uint64_t                        pcie_replay_count_acc;
+
+       /* PCIE replay rollover accumulated count */
+       uint64_t                        pcie_replay_rover_count_acc;
+
+       /* PCIE NAK sent  accumulated count */
+       uint32_t                        pcie_nak_sent_count_acc;
+
+       /* PCIE NAK received accumulated count */
+       uint32_t                        pcie_nak_rcvd_count_acc;
+
+       /* XGMI accumulated data transfer size(KiloBytes) */
+       uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
+       uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
+
+       /* PMFW attached timestamp (10ns resolution) */
+       uint64_t                        firmware_timestamp;
+
+       /* Current clocks (Mhz) */
+       uint16_t                        current_gfxclk[MAX_GFX_CLKS];
+       uint16_t                        current_socclk[MAX_CLKS];
+       uint16_t                        current_vclk0[MAX_CLKS];
+       uint16_t                        current_dclk0[MAX_CLKS];
+       uint16_t                        current_uclk;
+
+       uint16_t                        padding;
+};
+
 /*
  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
  * Use gpu_metrics_v2_1 or later instead.

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 602aa694123102346071c874d3d0fd8f5bb9c0d8..26d44a4370d23c901d0d02750f596a160f70d236 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -1052,6 +1052,9 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev)
        case METRICS_VERSION(1, 5):
                structure_size = sizeof(struct gpu_metrics_v1_5);
                break;
+       case METRICS_VERSION(1, 6):
+               structure_size = sizeof(struct gpu_metrics_v1_6);
+               break;
        case METRICS_VERSION(2, 0):
                structure_size = sizeof(struct gpu_metrics_v2_0);
                break;