drm/amd/display: Remove unused dcn_find_dcfclk_suits_all

dcn_find_dcfclk_suits_all() last use was removed by 2018's
commit 4fd994c448a3 ("drm/amd/display: Start using the new pp_smu
interface")

Remove it, and the dcn_find_normalized_clock_vdd_Level helper it used.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
index 39525721c976bc8f60091e9bd37a3df98b92fdd3..f1235bf9a5965f8b96875ea9856a30bc59d0ffe2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
@@ -1312,138 +1312,6 @@ bool dcn_validate_bandwidth(
                return false;
 }
 
-static unsigned int dcn_find_normalized_clock_vdd_Level(
-       const struct dc *dc,
-       enum dm_pp_clock_type clocks_type,
-       int clocks_in_khz)
-{
-       int vdd_level = dcn_bw_v_min0p65;
-
-       if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
-               return vdd_level;
-
-       switch (clocks_type) {
-       case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-               if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
-                       vdd_level = dcn_bw_v_max0p91;
-                       BREAK_TO_DEBUGGER();
-               } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
-                       vdd_level = dcn_bw_v_max0p9;
-               } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
-                       vdd_level = dcn_bw_v_nom0p8;
-               } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
-                       vdd_level = dcn_bw_v_mid0p72;
-               } else
-                       vdd_level = dcn_bw_v_min0p65;
-               break;
-       case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
-               if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
-                       vdd_level = dcn_bw_v_max0p91;
-                       BREAK_TO_DEBUGGER();
-               } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
-                       vdd_level = dcn_bw_v_max0p9;
-               } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
-                       vdd_level = dcn_bw_v_nom0p8;
-               } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
-                       vdd_level = dcn_bw_v_mid0p72;
-               } else
-                       vdd_level = dcn_bw_v_min0p65;
-               break;
-
-       case DM_PP_CLOCK_TYPE_DPPCLK:
-               if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
-                       vdd_level = dcn_bw_v_max0p91;
-                       BREAK_TO_DEBUGGER();
-               } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
-                       vdd_level = dcn_bw_v_max0p9;
-               } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
-                       vdd_level = dcn_bw_v_nom0p8;
-               } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
-                       vdd_level = dcn_bw_v_mid0p72;
-               } else
-                       vdd_level = dcn_bw_v_min0p65;
-               break;
-
-       case DM_PP_CLOCK_TYPE_MEMORY_CLK:
-               {
-                       unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
-
-                       if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
-                               vdd_level = dcn_bw_v_max0p91;
-                               BREAK_TO_DEBUGGER();
-                       } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
-                               vdd_level = dcn_bw_v_max0p9;
-                       } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
-                               vdd_level = dcn_bw_v_nom0p8;
-                       } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
-                               vdd_level = dcn_bw_v_mid0p72;
-                       } else
-                               vdd_level = dcn_bw_v_min0p65;
-               }
-               break;
-
-       case DM_PP_CLOCK_TYPE_DCFCLK:
-               if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
-                       vdd_level = dcn_bw_v_max0p91;
-                       BREAK_TO_DEBUGGER();
-               } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
-                       vdd_level = dcn_bw_v_max0p9;
-               } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
-                       vdd_level = dcn_bw_v_nom0p8;
-               } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
-                       vdd_level = dcn_bw_v_mid0p72;
-               } else
-                       vdd_level = dcn_bw_v_min0p65;
-               break;
-
-       default:
-                break;
-       }
-       return vdd_level;
-}
-
-unsigned int dcn_find_dcfclk_suits_all(
-       const struct dc *dc,
-       struct dc_clocks *clocks)
-{
-       unsigned vdd_level, vdd_level_temp;
-       unsigned dcf_clk;
-
-       /*find a common supported voltage level*/
-       vdd_level = dcn_find_normalized_clock_vdd_Level(
-               dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
-       vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-               dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
-
-       vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
-       vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-               dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
-       vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
-
-       vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-               dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
-       vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
-       vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-               dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
-
-       /*find that level conresponding dcfclk*/
-       vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
-       if (vdd_level == dcn_bw_v_max0p91) {
-               BREAK_TO_DEBUGGER();
-               dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
-       } else if (vdd_level == dcn_bw_v_max0p9)
-               dcf_clk =  dc->dcn_soc->dcfclkv_max0p9*1000;
-       else if (vdd_level == dcn_bw_v_nom0p8)
-               dcf_clk =  dc->dcn_soc->dcfclkv_nom0p8*1000;
-       else if (vdd_level == dcn_bw_v_mid0p72)
-               dcf_clk =  dc->dcn_soc->dcfclkv_mid0p72*1000;
-       else
-               dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;
-
-       DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);
-       return dcf_clk;
-}
-
 void dcn_bw_update_from_pplib_fclks(
        struct dc *dc,
        struct dm_pp_clock_levels_with_voltage *fclks)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
index 55529c5f471ce9917a7b52ebcbf022727d763c0b..d19a595c2be408347719b7f712f5175487a253b1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
@@ -624,10 +624,6 @@ bool dcn_validate_bandwidth(
                struct dc_state *context,
                bool fast_validate);
 
-unsigned int dcn_find_dcfclk_suits_all(
-       const struct dc *dc,
-       struct dc_clocks *clocks);
-
 void dcn_get_soc_clks(
                struct dc *dc,
                int *min_fclk_khz,