drm/i915/fbc: fix the implementation of wa_18038517565
authorVinod Govindapillai <vinod.govindapillai@intel.com>
Tue, 29 Jul 2025 12:46:48 +0000 (15:46 +0300)
committerTvrtko Ursulin <tursulin@ursulin.net>
Tue, 12 Aug 2025 08:05:07 +0000 (09:05 +0100)
commitfd56b9c9507f32b16159f9a922e1af5628254567
tree60239adc7e8dab7f6731e009be86bd742a1a2ae1
parent8f5ae30d69d7543eee0d70083daf4de8fe15d585
drm/i915/fbc: fix the implementation of wa_18038517565

As per the wa_18038517565, we need to disable FBC compressor
clock gating before enabling FBC and enable after disabling
FBC. Placing the enabling of clock gating in the fbc deactivate
function can make the above wa logic go wrong in case of
frontbuffer rendering FBC mechanism. FBC deactivate can get
called during fb invalidate and then the corresponding FBC
activate can get called without properly disabling the clock
gating and can result in compression stalled. So move the
enable clock gating at the end of one FBC session after FBC
is completely disabled for a pipe.

Bspec: 74212, 72197, 69741, 65555
Fixes: 010363c46189 ("drm/i915/display: implement wa_18038517565")
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250729124648.288497-1-vinod.govindapillai@intel.com
(cherry picked from commit 82dde0407ab126f8413fd6c51429e5057ced5ba2)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
drivers/gpu/drm/i915/display/intel_fbc.c