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x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN
authorTony Luck <tony.luck@intel.com>
Fri, 19 Mar 2021 17:39:19 +0000 (10:39 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 5 Feb 2022 11:37:55 +0000 (12:37 +0100)
commitfbdbf6743f777729aadd00c4444234770f8dd042
tree0b10faaf3e5fbae6fc055ad8809ed9ab6bc9e413tree
parentd4e4e61d4a5b87bfc9953c306a11d35d869417fdcommit | diff
x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN

commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream.

New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/x86/kernel/cpu/mce/intel.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)