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(parent: a99d744) | patch
clk: tegra: Use fence_udelay() during PLLU init
authorSowjanya Komatineni <skomatineni@nvidia.com>
Fri, 16 Aug 2019 19:41:58 +0000 (12:41 -0700)
committerThierry Reding <treding@nvidia.com>
Mon, 11 Nov 2019 13:53:03 +0000 (14:53 +0100)
commitf68cbb35788e3d4e76638e4cc4cc1df9cac03587
tree829932ccff4e39999af322a3e04db6acec2b71a1tree
parenta99d744d8c9ca7e00adeb14dd11971b4b5b8271fcommit | diff
clk: tegra: Use fence_udelay() during PLLU init

This patch uses fence_udelay rather than udelay during PLLU
initialization to ensure writes to clock registers happens before
waiting for specified delay.

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra210.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)