drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders
authorImre Deak <imre.deak@intel.com>
Tue, 16 Jun 2020 21:11:44 +0000 (00:11 +0300)
committerImre Deak <imre.deak@intel.com>
Tue, 23 Jun 2020 07:11:54 +0000 (10:11 +0300)
commitf153478de4b259afb0a383de83e817b4c237401b
tree7088a3d1c36b2a56a07b57f159cbfd39e6489cbc
parent8a25c4be583d8a9e38fbadcc49d4de32b1aa8906
drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders

MST encoders must use the master MST transcoder's DP_TP_STATUS and
DP_TP_CONTROL registers. Atm, during the HW readout of an MST encoder
connected to a slave transcoder we reset these register addresses in
intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register
addresses incorrectly; fix this.

One example where the above overwite happens is the encoder HW state
validation after enabling multiple streams; see
intel_dp_mst_enc_get_config(). After that during disabling any stream
we'll get a

'Timed out waiting for ACT sent when disabling'

error, due to reading from the incorrect DP_TP_STATUS register.

This change replaces
https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1
which just papered over the problem.

v2:
- Correct the failure scenario in the commit log. (José)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200616211146.23027-1-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_ddi.c