drm/i915/display: Load DP_TP_CTL/STATUS offset before use it
authorJosé Roberto de Souza <jose.souza@intel.com>
Tue, 14 Apr 2020 23:04:40 +0000 (16:04 -0700)
committerJosé Roberto de Souza <jose.souza@intel.com>
Fri, 17 Apr 2020 22:08:53 +0000 (15:08 -0700)
commitedcb9028d66b44d74ba4f8b9daa379b004dc1f85
tree5fb6ace7178c91d048cc47a57a9e6a8cd4ec7d79
parent0f8925090ac7ad451ed9e803662ebe3214dc8072
drm/i915/display: Load DP_TP_CTL/STATUS offset before use it

Right now dp.regs.dp_tp_ctl/status are only set during the encoder
pre_enable() hook, what is causing all reads and writes to those
registers to go to offset 0x0 before pre_enable() is executed.

So if i915 takes the BIOS state and don't do a modeset any following
link retraing will fail.

In the case that i915 needs to do a modeset, the DDI disable sequence
will write to a wrong register not disabling DP 'Transport Enable' in
DP_TP_CTL, making a HDMI modeset in the same port/transcoder to
not light up the monitor.

So here for GENs older than 12, that have those registers fixed at
port offset range it is loading at encoder/port init while for GEN12
it will keep setting it at encoder pre_enable() and during HW state
readout.

Fixes: 4444df6e205b ("drm/i915/tgl: move DP_TP_* to transcoder")
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200414230442.262092-1-jose.souza@intel.com
drivers/gpu/drm/i915/display/intel_ddi.c
drivers/gpu/drm/i915/display/intel_dp.c