drm/msm/hdmi: Manage HDMI PLL through PHY driver
authorArchit Taneja <architt@codeaurora.org>
Thu, 25 Feb 2016 05:52:39 +0000 (11:22 +0530)
committerRob Clark <robdclark@gmail.com>
Mon, 29 Feb 2016 14:48:30 +0000 (09:48 -0500)
commitea184891b60dd202aa151828c04ec7f7b97502e5
treea7a6f087beac52f44a25e8220b810fd811c28f66
parent15b4a452385955f3ae4477a079f02c5ff168d310
drm/msm/hdmi: Manage HDMI PLL through PHY driver

Add a helper to initialize PLL in the PHY driver. HDMI PLLs are going to
have their own mmio base different from that of PHY.

For the clock code in hdmi_phy_8960.c, some changes were needed for it to
work with the updated register offsets. Create a copy of the updated clock
code in hdmi_pll_8960.c, instead of rewriting it in hdmi_phy_8960.c
itself. This removes the need to place CONFIG_COMMON_CLOCK checks all
around, makes the code more legible, and also removes some old checkpatch
warnings with the original code.

The older hdmi pll clock ops in hdmi_phy_8960.c will be removed later. The
driver will use these until the HDMI PHY/PLL register offsets aren't
considered as separate domains (i.e. their offsets start from 0).

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/Makefile
drivers/gpu/drm/msm/hdmi/hdmi.h
drivers/gpu/drm/msm/hdmi/hdmi_phy.c
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c [new file with mode: 0644]