arm64: KVM: Add support for Stage-2 control of memory types and cacheability
authorMarc Zyngier <marc.zyngier@arm.com>
Fri, 6 Apr 2018 11:27:28 +0000 (12:27 +0100)
committerMarc Zyngier <marc.zyngier@arm.com>
Mon, 9 Jul 2018 10:37:41 +0000 (11:37 +0100)
commite48d53a91f6e90873e21a5ca5e8c0d7a9f8936a4
tree8226aa3bd5ae8eefb39ad90d66fff26917bd747b
parent1e4b044d22517cae7047c99038abb444423243ca
arm64: KVM: Add support for Stage-2 control of memory types and cacheability

Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes
results in the strongest attribute of the two stages.  This means
that the hypervisor has to perform quite a lot of cache maintenance
just in case the guest has some non-cacheable mappings around.

ARMv8.4 solves this problem by offering a different mode (FWB) where
Stage-2 has total control over the memory attribute (this is limited
to systems where both I/O and instruction fetches are coherent with
the dcache). This is achieved by having a different set of memory
attributes in the page tables, and a new bit set in HCR_EL2.

On such a system, we can then safely sidestep any form of dcache
management.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
arch/arm64/include/asm/cpucaps.h
arch/arm64/include/asm/kvm_arm.h
arch/arm64/include/asm/kvm_emulate.h
arch/arm64/include/asm/kvm_mmu.h
arch/arm64/include/asm/memory.h
arch/arm64/include/asm/pgtable-prot.h
arch/arm64/include/asm/sysreg.h
arch/arm64/kernel/cpufeature.c
virt/kvm/arm/mmu.c