clk: sunxi-ng: Add support for update bit
authorAndre Przywara <andre.przywara@arm.com>
Fri, 7 Mar 2025 00:26:17 +0000 (00:26 +0000)
committerChen-Yu Tsai <wens@csie.org>
Wed, 12 Mar 2025 03:58:09 +0000 (11:58 +0800)
commite16b9b71f40f603d5cbdcf02007c05ee03cb2be7
tree02724782b5507a753d5c23d064153caabf98f7b8
parentcdbb9d0d09db4cd09d23fec02d3b458664bc3d38
clk: sunxi-ng: Add support for update bit

Some clocks in the Allwinner A523 SoC contain an "update bit" (bit 27),
which must be set to apply any register changes, namely the mux
selector, the divider and the gate bit.

Add a new CCU feature bit to mark those clocks, and set bit 27 whenever
we are applying any changes.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307002628.10684-4-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
drivers/clk/sunxi-ng/ccu_common.h
drivers/clk/sunxi-ng/ccu_div.c
drivers/clk/sunxi-ng/ccu_gate.c
drivers/clk/sunxi-ng/ccu_mux.c