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i2c: piix4: Enable EFCH MMIO for Family 17h+
authorTerry Bowman <terry.bowman@amd.com>
Wed, 9 Feb 2022 17:27:17 +0000 (11:27 -0600)
committerWolfram Sang <wsa@kernel.org>
Thu, 10 Feb 2022 21:45:42 +0000 (22:45 +0100)
commite071ee718fbc8fcd897956ad8885de5d836202cf
treeb796a0e0bc0b83c30616562814200e58a4782727tree
parentc57a2d28c7aba10d6701e1efdb989a0bad3428bacommit | diff
i2c: piix4: Enable EFCH MMIO for Family 17h+

Enable EFCH MMIO using check for SMBus PCI revision ID value 0x51 or
greater. This PCI revision ID check will enable family 17h and future
AMD processors with the same EFCH SMBus controller HW.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
drivers/i2c/busses/i2c-piix4.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)