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(parent: d3c25dd) | patch
clk: renesas: r9a09g056: Add clock and reset entries for WDT controllers
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tue, 13 May 2025 15:46:34 +0000 (16:46 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 10 Jun 2025 08:20:45 +0000 (10:20 +0200)
commite018f9f8973760faacbdf9bf678fdb46c1f591c8
treeb97651937da043e53c7d17dada4d1eaafde05dfftree
parentd3c25dd1612da7ddf5857190e92b0c36d803c4d9commit | diff
clk: renesas: r9a09g056: Add clock and reset entries for WDT controllers

Add module clock and reset definitions for WDT0-3, which are available
on the RZ/V2N (R9A09G056) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g056-cpg.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)