net: enetc: cache accesses to &priv->si->hw
authorVladimir Oltean <vladimir.oltean@nxp.com>
Wed, 28 Sep 2022 09:52:02 +0000 (12:52 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 2 Dec 2022 16:40:02 +0000 (17:40 +0100)
commitde4dd4f9b3f648e07a2c3cc7115b655e02ac3672
tree4f4bb9d98ef1441957f61609a73fb4c5527247aa
parent1f080b8caae9bb59d5db89509f41e17f6d41edd2
net: enetc: cache accesses to &priv->si->hw

[ Upstream commit 715bf2610f1d1adf3d4f9b7b3dd729984ec4270a ]

The &priv->si->hw construct dereferences 2 pointers and makes lines
longer than they need to be, in turn making the code harder to read.

Replace &priv->si->hw accesses with a "hw" variable when there are 2 or
more accesses within a function that dereference this. This includes
loops, since &priv->si->hw is a loop invariant.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Stable-dep-of: 290b5fe096e7 ("net: enetc: preserve TX ring priority across reconfiguration")
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/net/ethernet/freescale/enetc/enetc.c
drivers/net/ethernet/freescale/enetc/enetc.h
drivers/net/ethernet/freescale/enetc/enetc_qos.c