clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
authorSam Shih <sam.shih@mediatek.com>
Sun, 17 Dec 2023 21:50:07 +0000 (21:50 +0000)
committerStephen Boyd <sboyd@kernel.org>
Wed, 3 Jan 2024 23:55:19 +0000 (15:55 -0800)
commitd9bf944beaaad1890ad3fcb755c61e1c7e4c5630
tree7f6edc3a36c29eefdb7458c3de837dda6c597b51
parentafd36e9d91b0a840983b829a9e95407d8151f7e7
clk: mediatek: add pcw_chg_bit control for PLLs of MT7988

Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
of the previously hardcoded PCW_CHG_MASK macro if set.
This will needed for clocks on the MT7988 SoC.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mediatek/clk-pll.c
drivers/clk/mediatek/clk-pll.h