drm/tegra: dc: Describe register copies
authorThierry Reding <treding@nvidia.com>
Mon, 8 Dec 2014 14:50:04 +0000 (15:50 +0100)
committerThierry Reding <treding@nvidia.com>
Tue, 27 Jan 2015 09:14:37 +0000 (10:14 +0100)
commitd700ba7a6657d7c2be76b56996f54f02783456a6
treebf88edff62c35373cc18aaa8978dc509940e6a05
parent42d0659ba76956665c704d2a7cee9fa0f54a7acf
drm/tegra: dc: Describe register copies

Most of the display controller's registers are double-buffered, a few of
them are triple-buffered. The ASSEMBLY shadow copy is latched intto the
ACTIVE copy for double-buffered registers. For triple-buffered registers
the ASSEMBLY copy is first latched into the ARM copy.

Latching into the ACTIVE copy happens immediately if the controller is
inactive. Otherwise the latching happens on the next frame boundary. The
latching of the ASSEMBLY into the ARM copy happens immediately. Latching
is controlled by a set of *_ACT_REQ and *_UPDATE bits in the
DC_CMD_STATE_CONTROL register.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/dc.c