drm/komeda: SW workaround for D71 doesn't flush shadow registers
authorLowry Li (Arm Technology China) <Lowry.Li@arm.com>
Fri, 6 Sep 2019 07:18:06 +0000 (07:18 +0000)
committerjames qian wang (Arm Technology China) <james.qian.wang@arm.com>
Fri, 27 Sep 2019 08:02:33 +0000 (16:02 +0800)
commitd6cb013579e743bc7bc5590ca35a1943f2b8f3c8
treee90caaa8352f70bdf6490d8a71542360f8ca8533
parent245f44e77101df44e1074c765732b5613579179d
drm/komeda: SW workaround for D71 doesn't flush shadow registers

This is a SW workaround for shadow un-flushed when together with the
DOU Timing-disable.

D71 HW doesn't update shadow registers when display output is turned
off. So when we disable all pipeline components together with display
output disabling by one flush or one operation, the disable operation
updated registers will not be flushed or valid in HW, which may lead
problem. To workaround this problem, introduce a two phase disable for
pipeline disable.

Phase1: Disable components with display is on and flush it, this phase
        for flushing or validating the shadow registers.
Phase2: Turn-off display output.

Signed-off-by: Lowry Li (Arm Technology China) <lowry.li@arm.com>
Reviewed-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com>
Signed-off-by: james qian wang (Arm Technology China) <james.qian.wang@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190906071750.4563-1-lowry.li@arm.com
drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c