drm/i915: Bump up CDCLK to eliminate underruns on TGL
authorStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Thu, 9 Jan 2020 22:05:47 +0000 (00:05 +0200)
committerJani Nikula <jani.nikula@intel.com>
Mon, 13 Jan 2020 11:44:11 +0000 (13:44 +0200)
commitd5848c4414a72107b2cfe71fb479d0cb832e0b1d
treebc739c14e921afaa4dfcaf9ec2df06801ba1a50d
parentaebf3b521b34ca49f6e81c667f92364334ca27cf
drm/i915: Bump up CDCLK to eliminate underruns on TGL

There seems to be some undocumented bandwidth
bottleneck/dependency which scales with CDCLK,
causing FIFO underruns when CDCLK is too low,
even when it's correct from BSpec point of view.

Currently for TGL platforms we calculate
min_cdclk initially based on pixel_rate divided
by 2, accounting for also plane requirements,
however in some cases the lowest possible CDCLK
doesn't work and causing the underruns.
We've found experimentally that raising cdclk to
at least  pixel_rate (rather than pixel_rate/2)
eliminates these underruns, so let's use this as a
temporary workaround until the hardware team
can suggest a more precise remedy.

Explicitly stating here that this seems to be currently
rather a Hack, than final solution.

v2: Use clamp operation instead of min(Matt Roper)

v3: - Fixed commit message(Matt Roper)
    - Now using pixel_rate instead of max_cdclk(Jani Nikula)
    - Switched to max from clamp(Ville Syrjälä)
    Hopefully this hybrid satisfies everyone :)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Closes: https://gitlab.freedesktop.org/drm/intel/issues/402
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200109220547.23817-1-stanislav.lisovskiy@intel.com
drivers/gpu/drm/i915/display/intel_cdclk.c