drm/i915/dmc: Do not enable the pipe DMC on TGL when PSR is possible
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 17 Jun 2025 17:07:59 +0000 (20:07 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 23 Jun 2025 14:50:07 +0000 (17:50 +0300)
commitcf899c0777b8d780dd6f82317bbe561deb6c7d1c
treed77b2402746a84217f29e85dd5bb1f193c2a6746
parent7a8ccadb5425bc42468d2866c1a5ad273cb2c2c3
drm/i915/dmc: Do not enable the pipe DMC on TGL when PSR is possible

On TGL/derivatives the pipe DMC state is lost when PG1 is disabled,
and the main DMC does not restore any of it. This means the state will
also be lost during PSR+DC5/6. It seems safest to not even enable the
pipe DMC in that case (the main DMC does restore the pipe DMC enable
bit in PIPEDMC_CONTROL_A for some reason).

Since pipe DMC is only needed for "fast LACE" on these platforms we aren't
actually losing anything here. In the future if we do want to enable
"fast LACE" we'll just have to remember that it won't be compatible with
PSR.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-10-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_dmc.c