riscv: misaligned: request misaligned exception from SBI
authorClément Léger <cleger@rivosinc.com>
Fri, 23 May 2025 10:19:23 +0000 (12:19 +0200)
committerPalmer Dabbelt <palmer@dabbelt.com>
Wed, 4 Jun 2025 22:11:03 +0000 (15:11 -0700)
commitcf5a8abc6560f989a880bec3647c614e638a0c9f
treec30f10cbae9a0fc6e997dd1c219d80cac836d203
parentc4a50db1e1739a5d4698dee7cd4c6f6430bff7b3
riscv: misaligned: request misaligned exception from SBI

Now that the kernel can handle misaligned accesses in S-mode, request
misaligned access exception delegation from SBI. This uses the FWFT SBI
extension defined in SBI version 3.0.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20250523101932.1594077-7-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
arch/riscv/include/asm/cpufeature.h
arch/riscv/kernel/traps_misaligned.c
arch/riscv/kernel/unaligned_access_speed.c