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(parent: c31b41f) | patch
drm/amd/display: Ammend DCPG IP control sequences to align with HW guidance
authorDillon Varone <dillon.varone@amd.com>
Tue, 14 Jan 2025 17:14:26 +0000 (12:14 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 13 Feb 2025 02:02:59 +0000 (21:02 -0500)
commitcbd97d621ece1d92c3542e52f8af7c04cd2c6afb
tree0a817d41aec02950b00a7f25fd71eed936f178b5tree
parentc31b41f1cb32450d8ac176eef9bda979760040e7commit | diff
drm/amd/display: Ammend DCPG IP control sequences to align with HW guidance

[WHY&HOW]
IP_REQUEST_CNTL should only be toggled off when it was originally, never
unconditionally.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c diff | blob | blame | history
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c diff | blob | blame | history
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h diff | blob | blame | history
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)