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(parent: 36dc177) | patch
drm/nouveau/mc/tu102: Fix MMU fault interrupts on Turing
authorAlistair Popple <apopple@nvidia.com>
Fri, 30 Oct 2020 02:36:41 +0000 (13:36 +1100)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 29 Jan 2021 06:49:12 +0000 (16:49 +1000)
commitc3cc12eaf511a8a47ade42f521534255ef8ffd47
tree7b80d10047986216e7e9fd8aff45a291c52b37eetree | snapshot
parent36dc1777ded32be541158c4c5be7626a153d0e06commit | diff
drm/nouveau/mc/tu102: Fix MMU fault interrupts on Turing

Turing reports MMU fault interrupts via new top level interrupt
registers. The old PMC MMU interrupt vector is not used by the HW. This
means we can remap the new top-level MMU interrupt to the exisiting PMC
MMU bit which simplifies the implementation until all interrupts are
moved over to using the new top level registers.

Signed-off-by: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c diff | blob | blame | history
drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)