drm/i915: cache hw power well enabled state
authorImre Deak <imre.deak@intel.com>
Thu, 5 Jun 2014 17:31:47 +0000 (20:31 +0300)
committerJani Nikula <jani.nikula@intel.com>
Mon, 23 Jun 2014 07:02:03 +0000 (10:02 +0300)
commitbfafe93a1cd466ef318b7e5f6c65f59aee147791
tree35ba06381f0cb31c9ed37c0216c98b7e8d739677
parenta497c3ba1d97fc69c1e78e7b96435ba8c2cb42ee
drm/i915: cache hw power well enabled state

Jesse noticed that the punit communication needed to query the VLV power
well status can cause substantial delays. Since we can query the state
frequently, for example during I2C transfers, maintain a cached version
of the HW state to get rid of this delay.

This fixes at least one reported regression where boot time increased by
~4 seconds due to frequent power well state queries on VLV during eDP
EDID read.

This regression has been introduced in

commit bb4932c4f17b68f34645ffbcf845e4c29d17290b
Author: Imre Deak <imre.deak@intel.com>
Date:   Mon Apr 14 20:24:33 2014 +0300

    drm/i915: vlv: check port power domain instead of only D0 for eDP VDD on

Reported-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_pm.c