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clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries
authorBiju Das <biju.das.jz@bp.renesas.com>
Mon, 25 Apr 2022 09:52:40 +0000 (10:52 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 28 Apr 2022 14:37:44 +0000 (16:37 +0200)
commitbe5b5fcbc779f04a6ad38e9d4772712fe05b6f15
tree787190745055ece2e120a85bdab7c039d84bc42dtree | snapshot
parenta9391e019015e96d4ed40587ce0f648edf1c32d3commit | diff
clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries

Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g043-cpg.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)