ASoC: rsnd: enable clk_i approximate rate usage
authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tue, 22 Aug 2023 23:50:31 +0000 (23:50 +0000)
committerMark Brown <broonie@kernel.org>
Wed, 23 Aug 2023 12:53:25 +0000 (13:53 +0100)
commitbd4cee2fdf69b56c2bf3e7ec7c2e12b81e08005c
treef3a615081f7469358aacceded2239700efa01caf
parent220adc0fda6bbc274fff5825e2fd7d3dcd719e5c
ASoC: rsnd: enable clk_i approximate rate usage

Basically Renesas sound ADG is assuming that it has accurately
divisible input clock. But sometimes / some board might not have it.
The clk_i from CPG is used for such case. It can't calculate accurate
division, but can be used as approximate rate.
This patch enable clk_i for such case.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Adnan Ali <adnan.ali@bp.renesas.com>
Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de>
Tested-by: Patrick Keil <patrick.keil@conti-engineering.com>
Link: https://lore.kernel.org/r/87msyizlfd.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sh/rcar/adg.c