clk: tegra: Init cfg structure in _get_pll_mnp
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Tue, 25 Jul 2017 10:34:06 +0000 (13:34 +0300)
committerStephen Boyd <sboyd@codeaurora.org>
Wed, 23 Aug 2017 22:59:15 +0000 (15:59 -0700)
commitbc7b34a2fb78661b2980d949aad8edc39c253e3a
treea518f04fca7e3146d3ba85d0f49550cb737155b1
parente34e69cc866a26ec42be789a49ea6174ddc801ca
clk: tegra: Init cfg structure in _get_pll_mnp

Not all fields are read from the hw depending on the PLL type. Make sure
the other fields are 0 by clearing the structure beforehand to prevent
users such as the rate re-calculation code from using bogus values.

Based on work by  Alex Frid <afrid@nvidia.com>

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/tegra/clk-pll.c