clk: renesas: rzv2h: Add support for RZ/G3E SoC
authorBiju Das <biju.das.jz@bp.renesas.com>
Fri, 13 Dec 2024 12:35:41 +0000 (12:35 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 7 Jan 2025 16:00:55 +0000 (17:00 +0100)
commitbb6a9aaf670735d6583c76073ec41190f5404dc5
tree6022c5340d86cf4597e388f45f7ae4c0d5a599ad
parent6b4a095cd537aade8c0e2dc1c17067e451a0cca1
clk: renesas: rzv2h: Add support for RZ/G3E SoC

The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with
more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1
are present only on the RZ/G3E SoC.

Add minimal clock and reset entries required to boot the Renesas RZ/G3E
SMARC EVK and binds it with the RZ/V2H CPG core driver.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241213123550.289193-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/Kconfig
drivers/clk/renesas/Makefile
drivers/clk/renesas/r9a09g047-cpg.c [new file with mode: 0644]
drivers/clk/renesas/rzv2h-cpg.c
drivers/clk/renesas/rzv2h-cpg.h