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(parent: 5e79cb2) | patch
irqchip: Add Layerscape SCFG MSI controller support
authorMinghuan Lian <Minghuan.Lian@nxp.com>
Wed, 23 Mar 2016 11:08:20 +0000 (19:08 +0800)
committerMarc Zyngier <marc.zyngier@arm.com>
Wed, 4 May 2016 08:58:04 +0000 (09:58 +0100)
commitb8f3ebe630a4f1b4ff9340103d3b565ad5d78d43
tree9072b01dd90206a5908274e8d91337c1ca41badftree | snapshot
parent5e79cb29ddbd1d354398308309337ba013245469commit | diff
irqchip: Add Layerscape SCFG MSI controller support

Some kind of Freescale Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
drivers/irqchip/Kconfig diff | blob | blame | history
drivers/irqchip/Makefile diff | blob | blame | history
drivers/irqchip/irq-ls-scfg-msi.c [new file with mode: 0644] blob
Linux 6.x block layer and io_uring tree(s)