drm/i915/display: Reset message bus after each read/write operation
authorMika Kahola <mika.kahola@intel.com>
Mon, 16 Oct 2023 12:55:44 +0000 (15:55 +0300)
committerMika Kahola <mika.kahola@intel.com>
Thu, 26 Oct 2023 14:48:14 +0000 (17:48 +0300)
commitb662c19654ca7fdb1dadd304ca3e26024fc89635
treef5fe560b450aff78f3c87db83aff589b6c3d7268
parenta1196dac2f504f89bc7941e8c63db50f1fe713f3
drm/i915/display: Reset message bus after each read/write operation

Every know and then we receive the following error when running
for example IGT test kms_flip.

[drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
[drm] *ERROR* PHY G Write 0d81 failed after 3 retries.

Since the error is sporadic in nature, the patch proposes
to reset the message bus after every successful or unsuccessful
read or write operation.

v2: Add FIXME's to indicate the experimental nature of
    this workaround (Rodrigo)
v3: Dropping the additional delay as moving reset to *_read_once()
    and *_write_once() functions seem unnecessary delay

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231016125544.719963-1-mika.kahola@intel.com
drivers/gpu/drm/i915/display/intel_cx0_phy.c