clk: tegra: pll: Adjust vco_min if SDM present
authorBill Huang <bilhuang@nvidia.com>
Thu, 18 Jun 2015 21:28:30 +0000 (17:28 -0400)
committerThierry Reding <treding@nvidia.com>
Thu, 17 Dec 2015 12:37:53 +0000 (13:37 +0100)
commitb5512b45d5ed699de328e17cd7c7027d89461920
treefbb0e8547493c65828b45fa0d80df76ee1669517
parent6929715cf6b944d8f88beb2aa25658084de106ab
clk: tegra: pll: Adjust vco_min if SDM present

This code makes use of the SDM fractional divider if present to
constrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.

Based on original work by Aleksandr Frid <afrid@nvidia.com>

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-pll.c
drivers/clk/tegra/clk.h