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(parent: df28e86) | patch
net: macb: Set MDIO clock divisor for pclk higher than 160MHz
authorBartosz Wawrzyniak <bwawrzyn@cisco.com>
Thu, 16 Mar 2023 10:03:39 +0000 (10:03 +0000)
committerDavid S. Miller <davem@davemloft.net>
Sun, 19 Mar 2023 08:39:21 +0000 (08:39 +0000)
commitb31587feaa0133b19a1900a26bce07a3c6d21af6
treec4949401f178536981907560e73a01aa58b6a347tree | snapshot
parentdf28e8690e7126fa5c99e8863c27574204589f31commit | diff
net: macb: Set MDIO clock divisor for pclk higher than 160MHz

Currently macb sets clock divisor for pclk up to 160 MHz.
Function gem_mdc_clk_div was updated to enable divisor
for higher values of pclk.

Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/cadence/macb.h diff | blob | blame | history
drivers/net/ethernet/cadence/macb_main.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)