octeontx2-pf: Use hardware register for CQE count
authorGeetha sowjanya <gakula@marvell.com>
Tue, 28 Sep 2021 05:55:26 +0000 (11:25 +0530)
committerDavid S. Miller <davem@davemloft.net>
Tue, 28 Sep 2021 13:10:24 +0000 (14:10 +0100)
commitaf3826db74d184bc9c2c9d3ff34548e5f317a6f3
tree836de45caa99a753010ba58e732f6d1969f731e5
parent13d45964c1b4cc8cc5b3693a4b2ba4992eea4370
octeontx2-pf: Use hardware register for CQE count

Current driver uses software CQ head pointer to poll on CQE
header in memory to determine if CQE is valid. Software needs
to make sure, that the reads of the CQE do not get re-ordered
so much that it ends up with an inconsistent view of the CQE.
To ensure that DMB barrier after read to first CQE cacheline
and before reading of the rest of the CQE is needed.
But having barrier for every CQE read will impact the performance,
instead use hardware CQ head and tail pointers to find the
valid number of CQEs.

Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h
include/linux/soc/marvell/octeontx2/asm.h