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(parent: 9311ed1) | patch
drm/amd/display: Clear DPCD lane settings after repeater training
authorShen, George <George.Shen@amd.com>
Tue, 16 Nov 2021 03:38:18 +0000 (22:38 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Dec 2021 21:05:26 +0000 (16:05 -0500)
commitaba3c3fede54e55573954fa7a7e28ec304557e50
tree6fc85a130507bfda83ebfb4983d931ff0f421678tree | snapshot
parent9311ed1e12417c81e1764d7656d97d9d459f9c5acommit | diff
drm/amd/display: Clear DPCD lane settings after repeater training

[Why]
VS and PE requested by repeater should not persist for the sink.

[How]
Clear DPCD lane settings after repeater link training finishes.

Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: George Shen <George.Shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c diff | blob | blame | history
Linux 6.x block layer and io_uring tree(s)