clk: mvebu: cp110: add sdio clock to cp-110 system controller
authorKonstantin Porotchkin <kostap@marvell.com>
Wed, 31 May 2017 13:19:15 +0000 (15:19 +0200)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Mon, 19 Jun 2017 15:22:23 +0000 (17:22 +0200)
commita45af6d3a98b4d8a2746de13a8db52fb4123bb56
treef550720166dbac486f76f1ee8e4f6b78994929dc
parent5ffeb5f5a77adc925699bbd9da198e5b8a4eec5a
clk: mvebu: cp110: add sdio clock to cp-110 system controller

This commit updates the CP110 system controller driver to add the
definition for a missing clock.

The SDIO clock is dedicated driving the SDHCI interface and its frequency
is 400MHz (2/5 of PLL source clock).

The SDIO interface should be bound to this clock and not the core clock
as in the older code.
Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while
the HW really supports up to 400 Mhz.

This patch also fixes the NAND clock relationship documentation.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[gregory.clement@free-electrons.com:
- use sdio instead of emmc to name the clock]
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
drivers/clk/mvebu/cp110-system-controller.c