drm/i915/dsc: Enable and disable appropriate power wells for VDSC
authorManasi Navare <manasi.d.navare@intel.com>
Wed, 28 Nov 2018 20:26:24 +0000 (12:26 -0800)
committerManasi Navare <manasi.d.navare@intel.com>
Thu, 29 Nov 2018 20:31:36 +0000 (12:31 -0800)
commita24c62f94be1a478ceb1086df726615a73a9e113
treef010d57fdfeb5b0060a124f69c4c4bcef3fce9cc
parenta600622c09ddf7da660ca714d5644ecf270426fc
drm/i915/dsc: Enable and disable appropriate power wells for VDSC

A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.

v4:
* Get VDSC power domain only if compression en is set
in crtc_state (Ville, Imre)
v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)

Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-13-manasi.d.navare@intel.com
drivers/gpu/drm/i915/intel_ddi.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_vdsc.c